The invention relates generally to low impedance output stage driver circuits and, more particularly, to a modification of a current-mode logic (CML) circuit which permits high fidelity amplification of high speed signals into low impedance loads using an output stage differential CML amplifier.
It is well known to use a so-called differential amplifier to amplify a differential signal, such as a signal that may be used in a high speed transfer of digital data. When bipolar junction n-p-n transistors are used, such an amplifier is made by tying the emitters of two transistors together. The differential input signals are applied to the bases of the two transistors, and amplified differential output signals are provided at the transistor collectors. This type of differential amplifier is called CML circuit.
CML circuits are often used to amplify differential digital signals, where the first digital signal is the complement of the second digital signal. A constant current source is connected to coupled emitters, and relatively small changes to the emitter-coupled transistor base currents cause the constant current to flow from one of the emitter-coupled transistors, to the other. That is, the output voltages rapidly change from high to low, or visa versa. A digital type on/off signal that is input into such a circuit will be amplified, with a change in the dc level.
The dc level change in the amplified signal is typically not desired, and these dc levels can be shifted using emitter follower amplifiers. Besides providing a dc level shift, this configuration of the differential amplifier, called an emitter-coupled logic (ECL) circuit, also provide a greater drive capacity to subsequently connected loads. However, the greater drive comes at the expense of frequency dependent amplifier impedances which causes infidelities in signal amplification, such as overshoot and ringing. To some extent the frequency dependent transfer characteristics of the transistor can be mitigated by operating the emitter followers at higher current levels. However, in integrated circuit (IC) design power consumption is critical.
FIG. 1 is a schematic diagram of an output CML circuit using ECL and CML circuits (prior art). The output circuit 10 comprises a pre-driver stage 12 and a final stage 14. The pre-driver stage 12 is an ECL circuit as described above, where Q3 and Q4 are emitter-coupled transistors, and Q1 and Q6 are emitter followers used to interface the pre-driver stage 12 with the final stage 14. Q5 and R4 act as a constant current source, while Q2/R1 and Q7/R5 are used to bias the emitter followers Q1 and Q6. The differential inputs A and A1 are connected, respectively, to the bases of Q3 and Q4 on lines 16 and 18. The pre-driver outputs N2 and N1 are on lines 20 and 22.
The final stage 14 is a CML circuit as described above. Q8 and Q9 are emitter-coupled transistors, while Q1/R8 acts as a constant current source. The inputs N2 and N1 are connected on lines 20 and 22, respectively with the bases of Q9 and Q8. The final stage outputs Y and Yn are connected on lines 24 and 26, respectively to Q9 and Q8. When the circuit of FIG. 1 is an output driver circuit to drive large loads, the resistances of R6 and R7 are low, for example, 50 ohms.
FIG. 2 is an exemplary signal diagram illustrating signal degradation in the amplification process (prior art). Signal A on line 16 is shown as an ideal digital signal with near-perfect rise and fall times, and no overshoot or excessive damping characteristics. Signal N1 is the amplified signal on line 22 that is normalized with respect to gain. Alternately, signal N2 could be displayed having a polarity opposite to the A signal. Amplification has introduced imperfect transitions. These imperfections are compounded in the next stage of amplification as shown in signal Y, which has also been normalized with respect to gain. Overshoot can be mitigated by biasing emitter follower transistors Q1 and Q6 to operate at a higher quiescent current level.
Slow rise and fall times seen at the transitions of signals N1 and Y of FIG. 2 are largely due to the so-called Miller-effect capacitance. The Miller-effect capacitance acts to vary to input capacitance from the base of a transistor to the collector in response to the voltage presented to the base, making the transistor input impedance vary with respect to the frequency of the input signal. As the voltage on the base increases, for example on Q8, the signal is amplified and the voltage on the collector simultaneously decreases. The Miller-effect capacitance causes an increased parasitic current flow from base to collector, in a sense acting as a larger capacitor, and taking away current that would otherwise flow into the base of Q8.
The overshoot and ringing seen at the transitions of signal Y of FIG. 2 are largely due to the use of emitter follower amplifiers Q1 and Q6 (FIG. 1). As mentioned above, the emitter follows are used to shift the dc level of the output signal and to increase high frequency gain between stages. However, the improved high frequency response comes at the price of frequency dependent gain that promotes ringing.
It is known to use feedback capacitors between the base and collector of a transistor to improve the flatten the frequency response of an amplifier. To some extent this feedback minimizes the signal degradation problems associated with the circuit of FIG. 1. Cross-coupled feedback capacitors have been used in differential amplifiers. For example, a capacitor from the base Q8 to the collector of Q9, and a capacitor from the base of Q9 to the collector of Q8. However, these solution typically come at the expense of diminished frequency response. It is also known to form a cascode transistor combination to form an amplifier with improved frequency response and less sensitivity to Miller-effect capacitance. Many high-speed communication processes require circuitry that generates clean waveforms, promoting quicker recognition to changes in state and more resistance to error in the transfer of data. Improvements in the waveforms produced by differential amplifier driver output circuitry are required to support the above-mentioned circuits.
It would be advantageous if the Miller-effect capacitance associated with the bases of emitter-coupled transistors in an output circuit CML differential amplifier could be eliminated.
It would be advantageous if CML stages could be coupled without the necessity of emitter follower amplifiers to provide cleaner output signal transitions with less overshoot and ringing.
It would be advantageous if signal integrity in the amplification of signals by a differential amplifier could be improved without increasing the operating currents of the drive circuitry.
Accordingly, an output driver circuit is provided comprising a final stage differential amplifier including emitter-coupled first and second transistors, and a pre-driver stage differential amplifier including emitter-coupled first and second transistors. A cascode is connected to the final stage differential amplifier to maintain a constant voltage at the collectors of the first and second transistors of the final stage differential amplifier.
The cascode is a pair of transistors cascoded with the differential amplifier. A first cascode transistor has a collector connected to Vcc through a first load resistor and an emitter connected to the collector of the final stage first transistor. A second cascode transistor has a collector connected to Vcc through a second load resistor and an emitter connected to the collector of the final stage second transistor.
The cascode also includes a first current bleeder transistor having a collector connected to the collector of the final stage first transistor and an emitter operatively connected to ground, and second current bleeder transistor having a collector connected to the collector of the final stage second transistor and an emitter operatively connected to ground.
A method is also provided for amplifying differential signals, the method comprising:
receiving a pair of differential input signals at a corresponding pair of circuit inputs;
differentially amplifying the voltage of the differential input signals;
simultaneously with the amplification of the differential input signals, eliminating any changes in the capacitance of the circuit inputs responsive to the amplification of the differential input signals; and
providing a pair of differential output signals which are amplified replicas of the corresponding differential input signals.
As in the above description of the circuit, the elimination of capacitance changes at the circuit inputs due to signal-amplification includes eliminating the Miller-effect capacitance at the bases of the final stage emitter-coupled transistors. The elimination of capacitance changes is accomplished in two sub-steps, comprising:
maintaining. a constant voltage at the collectors of the final stage emitter-coupled transistors; and.
bleeding current from the collectors of the final stage emitter-coupled transistors.